Thermal Management in PCB Design: Heat Sinks, Copper Pours and Thermal Vias

When I bring up a new IoT sensor node on the bench and the MCU is too hot to touch after ten minutes, I know the thermal design was treated as an afterthought. In compact, enclosure-sealed IoT hardware, heat has nowhere to go, and that trapped energy directly drives field failures — from drifting ADC readings and premature battery wear to solder joint fatigue and outright regulator shutdown. Over the last eight years designing battery-powered and mains-powered IoT boards, I've learned that effective thermal management isn't about bolting on a big heat sink at the end. It's about using the PCB itself as a heat spreader through deliberate copper pours, via arrays, and placement choices made on day one of layout. This article covers the practical techniques I apply to keep junction temperatures in check on cost-sensitive two- and four-layer boards without resorting to fans or exotic materials.

Why Compact IoT Boards Trap Heat and Where Failures Actually Start

In my experience, the thermal problems in IoT hardware are rarely caused by a single hot component. They come from the combination of small form factors, plastic enclosures with no airflow, and duty cycles that look low on paper but create sustained thermal loads in practice. A typical LoRaWAN or Wi-Fi sensor node might only transmit for a few seconds, but the buck converter, the 3.3V LDO feeding the radio, and the MCU itself dissipate heat continuously. Add solar charging or a USB-C input with a linear charger, and you have several watts to reject from a 40x60mm board sealed inside an IP65 box sitting in direct sun.

The failure mode I see most often is not catastrophic over-temperature shutdown, but slow degradation. Electrolytic capacitors near a hot buck inductor dry out twice as fast for every 10°C rise. A BME280 or SHT41 placed 5mm downwind of a regulator will read 2-3°C high, ruining your environmental data. And for battery-powered designs, elevated temperature accelerates self-discharge and permanently reduces lithium cell capacity. The Zephyr Project Documentation covers thermal mitigation strategies for sleep management, but the hardware still needs to keep the silicon cool enough that software throttling is a safety net, not the primary plan.

Mapping Your Real Power Dissipation

Before you draw a single copper pour, you need an honest power map. Don't rely on typical values from datasheets. Measure or calculate dissipation for each block under worst-case conditions: maximum input voltage, maximum load current, and maximum ambient temperature inside the enclosure, not outside. In one recent design for a solar-powered asset tracker, the nominal regulator loss was 0.3W at 12V input, but at 18V open-circuit from the panel on a cold morning, dissipation jumped to 0.72W — enough to push the SOT-23-5 package past 110°C.

I build a simple spreadsheet that lists every IC, its quiescent and active current, its package thermal resistance (Theta JA), and its expected rise above ambient. The key formula I use constantly is:

Tj = Ta + (Pd * Theta_JA)

Where Tj is junction temperature, Ta is local ambient inside the enclosure, Pd is power dissipated in the device, and Theta JA is junction-to-ambient thermal resistance. That Theta JA value assumes a standard JEDEC test board with a specific copper area, usually 1 sq inch of 1oz copper. Your tiny IoT board with minimal copper will be far worse unless you deliberately improve the heat path. That is exactly what copper pours and thermal vias are for.

The Enclosure Is Part of the Thermal Circuit

An IoT PCB does not cool to ambient air. It cools to the air trapped inside its enclosure, which itself slowly leaks heat to the outside world. I always add a 15-20°C derating for Ta when the board will live in a sealed polycarbonate box. If your spec says 45°C maximum outdoor temperature, design for a 65°C local ambient around the PCB. This one assumption has saved me from more than one respin.

Sizing Copper Pours and Planes to Spread Heat From Hot Components

Copper is the cheapest heat spreader you have. A solid pour connected to the thermal pad or ground pins of a hot component can cut Theta JA by 30-50% compared to minimal traces. The physics is straightforward: heat conducts laterally through the copper plane and then radiates and convects from a much larger surface area.

For power components like buck converters, LDOs, and charging ICs, I always create a dedicated copper pour on the same layer as the part, tied directly to its exposed pad or high-current pins, and then stitch it to a larger internal or bottom-layer plane with vias. On a two-layer board, this means pouring both top and bottom and stitching them. On a four-layer design, I tie the pour to an internal ground plane — which is far more effective because the plane is unbroken.

How large should the pour be? The benefit follows diminishing returns. Going from no pour to 100 mm² of 1oz copper drops Theta JA significantly. Doubling to 400 mm² helps again, but going to 1000 mm² adds little. For most IoT loads under 1.5W, I target 300-500 mm² of copper per watt of dissipation on the primary heat-spreading layer. If you are tight on space, even 150-200 mm² is worth doing.

Copper Weight and Thermal Relief Trade-offs

I've found that moving from 1oz to 2oz copper is one of the most cost-effective thermal upgrades for two-layer IoT boards. The added weight roughly doubles lateral thermal conductivity and adds only a small premium at most fabs. For higher-power designs, like a gateway with a 2A LTE module, I specify 2oz outer layers as standard.

Be careful with thermal relief spokes on pads that need to conduct heat. For a QFN thermal pad or a DPAK tab that is meant to be a heat path, I use solid or 4-spoke 0.4mm wide connections, not the default thin thermal relief. Otherwise you create a bottleneck right where you need conductivity. I keep thermal relief for hand-soldered passive components, but I remove it on power thermal pads. This is a setting you control in your pour properties, and it is worth checking with your assembler if you plan to use solid connections with reflow — they often prefer at least minimal relief to avoid tombstoning, but for a large exposed pad, solid is usually fine with proper paste coverage.

When you are starting your layout, getting the PCB Design Basics with KiCad: Schematic to Board Layout flow right helps here, because you want to define these pour areas early and assign them correct net priorities so small signal pours don't fragment your main heat spreader.

# Quick junction temperature estimator (Python)
# Use this to check if your copper strategy is enough

def junction_temp(power_w, theta_ja_c_per_w, ambient_c):
    return ambient_c + (power_w * theta_ja_c_per_w)

# Example: MP1584 buck, 0.6W loss, SOT-23 with 80 C/W on minimal copper
# vs. 45 C/W on board with 400mm2 pour + stitched plane
ta_enclosure = 65.0  # degC inside sealed box

tj_minimal = junction_temp(0.6, 80, ta_enclosure)
tj_poured  = junction_temp(0.6, 45, ta_enclosure)

print(f"Minimal copper Tj: {tj_minimal:.1f} C")  # 113.0 C - too close to limit
print(f"With pour + vias Tj: {tj_poured:.1f} C") # 92.0 C - safe margin

# For 2oz copper, reduce Theta JA by ~15% as rough estimate
tj_2oz = junction_temp(0.6, 45 * 0.85, ta_enclosure)
print(f"With 2oz pour Tj: {tj_2oz:.1f} C")       # 87.9 C

Thermal Via Arrays That Move Heat Between Layers Instead of Trapping It

If copper pours spread heat sideways, thermal vias move it vertically. A via array under a thermal pad connects the top-side heat source to internal planes and to the bottom-side copper where the heat can spread further and couple to the enclosure or to air. Without vias, a top-layer pour is largely isolated from the rest of the board stack by FR-4, which is a terrible thermal conductor at about 0.3 W/mK compared to copper at 385 W/mK.

The biggest mistake I see is using too few vias, or placing them outside the pad where they do little good. For a QFN or DFN with an exposed pad, the vias must be inside the pad itself. This requires via-in-pad with plugged or tented vias to avoid solder wicking during reflow. Most modern fabs handle this well at low cost if you specify "vias plugged and capped" or at minimum "tented vias." For larger DPAK or TO-252 packages, I place vias directly in the tab area and just outside its edge.

Via Diameter, Pitch, and Fill Choices I Use

Through my own testing and cross-checking with thermal camera measurements, I've settled on a consistent pattern: 0.3mm drill (0.5-0.6mm finished pad) vias on a 1.0-1.2mm pitch in a grid under the thermal pad. Smaller drills are more prone to being incompletely plated if the board is thick, while larger drills (0.5mm+) can wick too much solder. Pitch tighter than 0.8mm gives diminishing returns and can weaken the pad structurally.

For unfilled vias, the air inside limits conductivity. Filling with conductive epoxy helps but is expensive and rarely needed for IoT power levels under 3W. What I do specify is that the vias should not have thermal relief on internal planes — use direct solid connections. A thermal relief gap on a via defeats the entire purpose.

Remember to add solder mask clearance over the bottom-side copper that your vias connect to. If that copper is covered by mask, it will not radiate well and will not couple to a heat sink or enclosure wall. On some designs I leave the bottom-side heat spreader copper exposed and add a thin silicone thermal pad to the enclosure base to create a direct conduction path.

// Zephyr: simple on-board thermistor readout for thermal throttling
// Assumes NTC on ADC channel + moving average
// References: Zephyr Project Documentation ADC API

#include <zephyr/drivers/adc.h>
#include <zephyr/kernel.h>

#define ADC_NODE DT_NODELABEL(adc1)
static const struct adc_dt_spec therm_spec = ADC_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), 0);

int read_board_temp_celsius(int *temp_c) {
    int16_t buf;
    struct adc_sequence seq = {
        .buffer = &buf,
        .buffer_size = sizeof(buf),
        .calibrate = true,
    };
    adc_sequence_init_dt(&therm_spec, &seq);
    int ret = adc_read(therm_spec.dev, &seq);
    if (ret != 0) return ret;

    int32_t mv = buf;
    adc_raw_to_millivolts_dt(&therm_spec, &mv);
    // Example: 10k NTC, divider with 10k to 3.3V, Steinhart-Hart simplified
    // Convert mv to resistance, then to temp. Calibrate for your NTC.
    int32_t r_ntc = (10000 * mv) / (3300 - mv);
    // Placeholder linear approx: replace with lookup table
    *temp_c = 25 + (10000 - r_ntc) / 400;
    return 0;
}

void thermal_task(void) {
    int temp;
    while (1) {
        if (read_board_temp_celsius(&temp) == 0 && temp > 75) {
            // Throttle radio TX duty cycle or reduce CPU freq
            k_sleep(K_MSEC(5000));
        }
        k_sleep(K_MSEC(1000));
    }
}

Selecting and Mounting Heat Sinks When Every Millimeter Counts

On many IoT boards you can avoid a heat sink entirely with good copper and via design. But when you have a concentrated 1.5W+ source — a PoE regulator, a 2A battery charger, or an embedded SoC like an i.MX or Raspberry Pi CM4 — you will need one. The challenge is that IoT enclosures leave almost no headroom, and adhesive-mounted sinks can fall off in the field.

I prefer low-profile, stamped aluminum or copper heat sinks with a footprint that matches the IC package plus a 2-3mm overhang. For a QFN buck converter in a small node, a 15x15x5mm sink with adhesive thermal tape can drop the junction temperature another 10-15°C when it has even a small airflow gap to the enclosure wall. But in a fully sealed box, that sink is just heating the trapped air. In that case I design the sink to press against the enclosure wall through a compressible gap pad, turning the entire case into a radiator.

Attachment Methods That Survive Vibration

In my experience, push-pin and clip-mounted sinks are underused in IoT designs because they need mounting holes. They are far more reliable than adhesive tape alone, especially for devices mounted on machinery or vehicles. I add two 1.6mm non-plated holes spaced for a standard clip if the board will see vibration. If you must use adhesive, choose an acrylic-based thermal tape rated for 100°C+ and ensure both surfaces are cleaned with isopropyl before assembly. The Design for Manufacturing: PCB Rules That Reduce Assembly Defects guide is worth reviewing here, because via-in-pad and sink attachment are exactly the details that cause assembly issues when not communicated clearly to the fab.

Don't forget to check your keepouts. A heat sink over a radio module can detune the antenna or add loss. I keep at least 8-10mm clearance between a sink and any PCB Antenna Design for IoT: Trace Antennas, Matching Networks and Layout Rules keepout zone, and I never place a metal sink directly over a GNSS or Wi-Fi trace antenna — that is a guaranteed range reduction.

When a Copper Coin or Thick Copper Actually Helps

For boards with a single very hot spot, like a PoE PD controller dissipating 2W in a small area, I have used embedded copper coins — a solid copper slug pressed into a routed cavity in the PCB that conducts directly from the IC pad to a bottom-side plane or sink. This provides lower thermal resistance than dozens of vias, but it adds cost and requires a specialized fab process. I reserve it for industrial gateways and edge compute nodes where reliability justifies the price. For most sensor nodes, a dense via array with 2oz copper gets you 80% of the benefit at a fraction of the cost.

Stackup and Component Placement Strategies for Low-Cost Thermal Control

The cheapest thermal upgrade is often a smarter stackup and better placement, not more copper weight. On a four-layer IoT board I use this stack whenever possible: Layer 1 (top) signal + power pours, Layer 2 solid ground plane, Layer 3 power or ground, Layer 4 signal + copper spreader. The uninterrupted ground plane on Layer 2 acts as a superb lateral heat spreader because it is continuous under all components. Avoid splitting it with long traces; route those on Layer 3 or 4 instead.

On cost-sensitive two-layer boards where I cannot have an internal plane, I flood both layers with ground copper and stitch them with vias every 8-10mm across the entire board. This creates a pseudo-plane that spreads heat far better than isolated islands. I also widen the ground return paths from hot components — those traces are thermal paths too.

Placement Rules I Follow for Hot Parts

I place high-dissipation parts near board edges or near mounting holes that provide a mechanical thermal path to the enclosure. Center-mounted hot parts heat the whole board uniformly, while edge-placed parts can dump heat along two directions and couple to standoffs. I never place temperature sensors, crystal oscillators, or RF matching networks downwind of a regulator's airflow path — even natural convection inside a small box has a direction.

Spacing matters more than people think. Putting two 0.5W regulators 3mm apart creates a combined hot spot that is hotter than one 1W device, because their thermal spreading circles overlap. I keep at least 10-15mm separation between independent power stages. If space forces them close, I add a narrow slot or at least avoid merging their copper pours so each has its own spreading area.

For power integrity and thermal overlap, the guidance in Power Supply Design for Embedded Systems: LDO, Buck Converter and Battery Management pairs well with thermal planning — the input and output capacitors for a buck converter need to be close electrically, but you can still orient the inductor and diode so their heat doesn't crowd the controller IC.

-- KiCad footprint trick: thermal via array under QFN exposed pad
-- Add to footprint file (.kicad_mod) or place manually with array tool
-- This is a 3x3 grid, 0.3mm drill, 1.0mm pitch, inside 4.0x4.0mm EP

(pad "EP" smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask F.Paste)
  (thermal_bridge_angle 45) (zone_connect 2)  # solid connection for heat
)

# Via array (through, 0.6mm pad, 0.3mm drill, no solder mask tenting on bottom)
# Place vias centered, ensure "pad connections: solid" on inner layers
# Example coordinates for 3x3 grid, pitch 1.0mm:
(via (at -1 -1) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 0 -1) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 1 -1) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at -1 0) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 0 0) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 1 0) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at -1 1) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 0 1) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 1 1) (size 0.6) (drill 0.3) (layers F.Cu B.Cu) (net 0))

# Tip: set solder mask expansion 0 and specify "vias tented on top, open on bottom"
# at fab so bottom copper spreads heat to air or gap pad

Validating Thermal Performance on the Bench Without a Thermal Chamber

You do not need a $20k thermal chamber to find problems. With a $300 thermal camera dongle for a phone, a thermocouple, and a controlled load, you can validate most IoT designs on the bench. My standard process is to run the board inside its actual enclosure, with the lid on, at maximum load, for at least 30 minutes to reach steady state. I log temperature with at least two points: a thermocouple taped to the top of the hottest IC (with a tiny dot of thermal grease and Kapton tape), and an NTC already on the board that firmware can log over UART.

I also check for hidden hot spots that don't show up on a single IC measurement. A current sense resistor, a reverse polarity MOSFET, or a small ferrite bead can dissipate surprising power. On one LoRa field unit, a 50mΩ sense resistor at 1.2A was dropping 72mW, but its 0603 package reached 85°C because it had almost no copper connection. Enlarging its pads to pours and adding two vias beside it dropped it to 55°C.

Building a Simple Thermal Test in Firmware

For boards running FreeRTOS or Zephyr, I add a test mode that exercises all peripherals at once — radio transmitting at max power, LEDs on, sensors polling, flash writing — to create the worst-case sustained load that normal application code might only hit briefly. The FreeRTOS Documentation covers the task and timer features that make it easy to create this load pattern without modifying production code.

Log temperature and load current to a CSV file every second. Plot Tj versus time. If the curve has not flattened after 20 minutes, you haven't reached steady state. I also repeat the test with the board resting on a wooden bench versus suspended in air versus mounted to a metal plate. The difference shows how much conduction through mounting points matters for your enclosure.

What to Fix When Temperatures Are Too High

If your validation shows a 15°C overshoot, don't jump straight to a heat sink. First, verify your copper pours are actually pouring. In KiCad and Altium I have often seen pours blocked by a thin keepout or by orphaned net ties that isolate the pour island. Use the 3D viewer and the net connectivity highlighter to confirm the pour is solidly tied to the thermal pad or ground pins with multiple vias, not a single narrow trace.

Second, check that internal planes are not cut by routing. A single trace cutting across your ground plane can create a thermal bottleneck as effectively as an electrical one. Rip up a few traces and reroute them on another layer to keep the plane continuous under the hot zone. For high-speed designs you need that plane for Signal Integrity for High-Speed PCB: Impedance Control, Crosstalk and EMI as well, so fixing the thermal cut often fixes signal issues too.

Finally, if you do need a mechanical fix, adding a 0.5mm silicone gap pad between the bottom-side copper spreader and the aluminum enclosure base is often more effective than a taller finned sink inside a sealed box. The gap pad conducts directly to the outside world, while a finned sink just recirculates hot air inside. I've measured 12-18°C improvements from a $0.30 gap pad alone when the enclosure is metal.

Frequently Asked Questions